// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_rtsq_s_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:25:28 Create file
// ******************************************************************************

#ifndef __STARS_RTSQ_S_REG_REG_OFFSET_H__
#define __STARS_RTSQ_S_REG_REG_OFFSET_H__

/* STARS_RTSQ_S_REG Base address of Module's Register */
#define SOC_STARS_RTSQ_S_REG_BASE                       (0x4004000)

/******************************************************************************/
/*                      SOC STARS_RTSQ_S_REG Registers' Definitions                            */
/******************************************************************************/

#define SOC_STARS_RTSQ_S_REG_STARS_VFG_SEC_REG                      (SOC_STARS_RTSQ_S_REG_BASE + 0x10)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_0_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x14)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_1_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x18)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_2_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x1C)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_3_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x20)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_4_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x24)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_5_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x28)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_6_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x2C)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_7_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x30)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_8_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x34)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_9_REG                  (SOC_STARS_RTSQ_S_REG_BASE + 0x38)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_10_REG                 (SOC_STARS_RTSQ_S_REG_BASE + 0x3C)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_11_REG                 (SOC_STARS_RTSQ_S_REG_BASE + 0x40)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_12_REG                 (SOC_STARS_RTSQ_S_REG_BASE + 0x44)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_13_REG                 (SOC_STARS_RTSQ_S_REG_BASE + 0x48)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_14_REG                 (SOC_STARS_RTSQ_S_REG_BASE + 0x4C)  
#define SOC_STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_15_REG                 (SOC_STARS_RTSQ_S_REG_BASE + 0x50)  
#define SOC_STARS_RTSQ_S_REG_STARS_SWAPBUF_NS_AXPROT_SETTING3_REG   (SOC_STARS_RTSQ_S_REG_BASE + 0x800) 
#define SOC_STARS_RTSQ_S_REG_STARS_SWAPBUF_S_AXPROT_SETTING3_REG    (SOC_STARS_RTSQ_S_REG_BASE + 0x804) 
#define SOC_STARS_RTSQ_S_REG_STARS_SWAPBUF_NS_SETTING1_REG          (SOC_STARS_RTSQ_S_REG_BASE + 0x808) 
#define SOC_STARS_RTSQ_S_REG_STARS_SWAPIN_CTRL0_S_REG               (SOC_STARS_RTSQ_S_REG_BASE + 0x900) 
#define SOC_STARS_RTSQ_S_REG_STARS_SWAPIN_CTRL1_S_REG               (SOC_STARS_RTSQ_S_REG_BASE + 0x904) 
#define SOC_STARS_RTSQ_S_REG_STARS_SWAPIN_CTRL2_S_REG               (SOC_STARS_RTSQ_S_REG_BASE + 0x908) 
#define SOC_STARS_RTSQ_S_REG_STARS_S_SQ_SWAP_BUF_BASE_ADDR_CFG0_REG (SOC_STARS_RTSQ_S_REG_BASE + 0xA00) 
#define SOC_STARS_RTSQ_S_REG_STARS_S_SQ_SWAP_BUF_BASE_ADDR_CFG1_REG (SOC_STARS_RTSQ_S_REG_BASE + 0xA04) 

#endif // __STARS_RTSQ_S_REG_REG_OFFSET_H__
